? semiconductor components industries, llc, 2003 july, 2003 - rev. 4 1 publication order number: mc74vhc00/d mc74vhc00 quad 2-input nand gate the mc74vhc00 is an advanced high speed cmos 2-input nand gate fabricated with silicon gate cmos technology. it achieves high speed operation similar to equivalent bipolar schottky ttl while maintaining cmos low power dissipation. the internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. the inputs tolerate voltages up to 7 v, allowing the interface of 5 v systems to 3 v systems. ? high speed: t pd = 3.7 ns (typ) at v cc = 5 v ? low power dissipation: i cc = 2 a (max) at t a = 25 c ? high noise immunity: v nih = v nil = 28% v cc ? power down protection provided on inputs ? balanced propagation delays ? designed for 2 v to 5.5 v operating range ? low noise: v olp = 0.8 v (max) ? pin and function compatible with other standard logic families ? latchup performance exceeds 300 ma ? esd performance: hbm > 2000 v; machine model > 200 v ? chip complexity: 32 fets or 8 equivalent gates figure 1. pinout: 14 - lead packages (top view) 13 14 12 11 10 9 8 2 1 34567 v cc b4 a4 y4 b3 a3 y3 a1 b1 y1 a2 b2 y2 gnd l l h h l h l h function table inputs output ab h h h l y a = assembly location l, wl = wafer lot y = year w, ww = work week marking diagrams device package shipping ordering information mc74vhc00dr2 so-14 2500 tape & reel mc74vhc00dt tssop-14 96 units/rail mc74vhc00dtr2 tssop-14 2500 tape & reel MC74VHC00MEL eiaj so - 14 2000 tape & reel so - 14 d suffix case 751a - 03 tssop - 14 dt suffix case 948g - 01 eiaj so - 14 m suffix case 965 - 01 14 1 14 1 1 14 vhc00 awlyww vhc00 awlyww vhc00 alyw http://onsemi.com
mc74vhc00 http://onsemi.com 2 3 y1 1 a1 figure 2. logic diagram 2 b1 6 y2 4 a2 5 b2 8 y3 9 a3 10 b3 11 y4 12 a4 13 b4 y = ab maximum ratings (note 1) symbol parameter value unit v cc positive dc supply voltage - 0.5 to +7.0 v v in digital input voltage - 0.5 to +7.0 v v out dc output voltage - 0.5 to v cc +0.5 v i ik input diode current -20 ma i ok output diode current 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 75 ma p d power dissipation in still air soic package tssop 200 180 mw t stg storage temperature range - 65 to +150 c v esd esd withstand voltage human body model (note 2) machine model (note 3) charged device model (note 4) >2000 >200 n/a v i latch - up latch- up performance above v cc and below gnd at 125 c (note 5) 300 ma ja thermal resistance, junction to ambient soic package tssop 143 164 c/w 1. maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to th e recommended operating conditions. 2. tested to eia/jesd22 - a114 - a 3. tested to eia/jesd22 - a115 - a 4. tested to jesd22 - c101- a 5. tested to eia/jesd78 recommended operating conditions symbol characteristics min max unit v cc dc supply voltage 2.0 5.5 v v in dc input voltage 0 5.5 v v out dc output voltage 0 v cc v t a operating temperature range, all package types -55 125 c t r , t f input rise or fall time v cc = 3.3 v + 0.3 v v cc = 5.0 v + 0.5 v 0 0 100 20 ns/v
mc74vhc00 http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? dc electrical characteristics ???? ? ?? ? ???? ?????? ? ???? ? ?????? ??????? ? ????? ? ??????? ???? ? ?? ? ???? v cc ??????? ?????? ? ??????? t a = 25 c ????? ? ??? ? ????? t a = - 40 to 85 c ????? ? ??? ? ????? t a = - 55 to +125 c ?? ?? ?? ???? ???? symbol ?????? ?????? parameter ??????? ??????? test conditions ???? ???? v cc v ??? ??? min ??? ??? typ ??? ??? max ??? ??? min ??? ??? max ??? ??? min ??? ??? max ?? ?? unit ???? ? ?? ? ???? v ih ?????? ? ???? ? ?????? high- level input voltage ??????? ? ????? ? ??????? ???? ? ?? ? ???? 2.0 3.0 to 5.5 ??? ?? ? ??? 1.50 v cc x 0.7 ??? ? ? ? ??? ??? ? ? ? ??? ??? ? ? ? ??? 1.50 v cc x 0.7 ??? ? ? ? ??? ??? ? ? ? ??? 1.50 v cc x 0.7 ??? ? ? ? ??? ?? ?? ?? v ???? ? ?? ? ???? v il ?????? ? ???? ? ?????? low - level input voltage ??????? ? ????? ? ??????? ???? ? ?? ? ???? 2.0 3.0 to 5.5 ??? ?? ? ??? ??? ? ? ? ??? ??? ? ? ? ??? 0.50 v cc x 0.3 ??? ? ? ? ??? ??? ? ? ? ??? 0.50 v cc x 0.3 ??? ? ? ? ??? ??? ? ? ? ??? 0.50 v cc x 0.3 ?? ?? ?? v ???? ? ?? ? ? ?? ? ???? v oh ?????? ? ???? ? ? ???? ? ?????? high- level output voltage ??????? ? ????? ? ? ????? ? ??????? v in = v ih or v il i oh = - 50 a ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 ??? ?? ? ?? ? ??? 1.9 2.9 4.4 ??? ? ? ? ? ? ? ??? 2.0 3.0 4.5 ??? ? ? ? ? ? ? ??? ??? ? ? ? ? ? ? ??? 1.9 2.9 4.4 ??? ? ? ? ? ? ? ??? ??? ? ? ? ? ? ? ??? 1.9 2.9 4.4 ??? ? ? ? ? ? ? ??? ?? ?? ?? ?? v ???? ? ?? ? ? ?? ? ???? ?????? ? ???? ? ? ???? ? ?????? ??????? ? ????? ? ? ????? ? ??????? v in = v ih or v il i oh = - 4 ma i oh = - 8 ma ???? ? ?? ? ? ?? ? ???? 3.0 4.5 ??? ?? ? ?? ? ??? 2.58 3.94 ??? ? ? ? ? ? ? ??? ??? ? ? ? ? ? ? ??? ??? ? ? ? ? ? ? ??? 2.48 3.80 ??? ? ? ? ? ? ? ??? ??? ? ? ? ? ? ? ??? 2.40 3.70 ??? ? ? ? ? ? ? ??? ?? ?? ?? ?? ???? ? ?? ? ???? v ol ?????? ? ???? ? ?????? low - level output voltage ??????? ? ????? ? ??????? v in = v ih or v il i ol = 50 a ???? ? ?? ? ???? 2.0 3.0 4.5 ??? ?? ? ??? ??? ? ? ? ??? 0.0 0.0 0.0 ??? ? ? ? ??? 0.1 0.1 0.1 ??? ? ? ? ??? ??? ? ? ? ??? 0.1 0.1 0.1 ??? ? ? ? ??? ??? ? ? ? ??? 0.1 0.1 0.1 ?? ?? ?? v ???? ? ?? ? ???? ?????? ? ???? ? ?????? ??????? ? ????? ? ??????? v in = v ih or v il i ol = 4 ma i ol = 8 ma ???? ? ?? ? ???? 3.0 4.5 ??? ?? ? ??? ??? ? ? ? ??? ??? ? ? ? ??? 0.36 0.36 ??? ? ? ? ??? ??? ? ? ? ??? 0.44 0.44 ??? ? ? ? ??? ??? ? ? ? ??? 0.55 0.55 ?? ?? ?? ???? ? ?? ? ???? i in ?????? ? ???? ? ?????? input leakage current ??????? ? ????? ? ??????? v in = 5.5 v or gnd ???? ? ?? ? ???? 0 to 5.5 ??? ?? ? ??? ??? ? ? ? ??? ??? ? ? ? ??? 0.1 ??? ? ? ? ??? ??? ? ? ? ??? 1.0 ??? ? ? ? ??? ??? ? ? ? ??? 2.0 ?? ?? ?? a ???? ? ?? ? ???? i cc ?????? ? ???? ? ?????? quiescent supply current ??????? ? ????? ? ??????? v in = v cc or gnd ???? ? ?? ? ???? 5.5 ??? ?? ? ??? ??? ? ? ? ??? ??? ? ? ? ??? 2.0 ??? ? ? ? ??? ??? ? ? ? ??? 20 ??? ? ? ? ??? ??? ? ? ? ??? 40 ?? ?? ?? a ????????????????????????????????? ac electrical characteristics (input t r = t f = 3.0 ns) ???? ? ?? ? ???? ?????? ? ???? ? ?????? ?????????? ? ???????? ? ?????????? ??????? ? ????? ? ??????? t a = 25 c ????? ? ??? ? ????? t a = - 40 to 85 c ????? ? ??? ? ????? t a = - 55 to +125 c ?? ?? ?? ???? ???? symbol ?????? ?????? parameter ?????????? ?????????? test conditions ??? ??? min ??? ??? typ ??? ??? max ??? ??? min ??? ??? max ??? ??? min ??? ??? max ?? ?? unit ???? ? ?? ? ???? t plh , t phl ?????? ? ???? ? ?????? propagation delay, a or b to y ?????????? ? ???????? ? ?????????? v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ??? ? ? ? ??? 5.5 8.0 ??? ? ? ? ??? 7.9 11.4 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 9.5 13.0 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 10 14.5 ?? ?? ?? ns ???? ???? ?????? ?????? ?????????? ?????????? v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf ??? ??? ??? ??? 3.7 5.2 ??? ??? 5.5 7.5 ??? ??? 1.0 1.0 ??? ??? 6.5 8.5 ??? ??? 1.0 1.0 ??? ??? 7.0 9.5 ?? ?? ???? ? ?? ? ???? c in ?????? ? ???? ? ?????? input capacitance ?????????? ? ???????? ? ?????????? ??? ? ? ? ??? ??? ? ? ? ??? 4.0 ??? ? ? ? ??? 10 ??? ? ? ? ??? ??? ? ? ? ??? 10 ??? ? ? ? ??? ??? ? ? ? ??? 10 ?? ?? ?? pf typical @ 25 c, v cc = 5.0 v c pd power dissipation capacitance (note 6) 19 pf 6. c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption with out load. average operating current can be obtained by the equation: i cc(opr ) = c pd v cc f in + i cc / 4 (per gate). c pd is used to determine the no - load dynamic power consumption; p d = c pd v cc 2 f in + i cc v cc . noise characteristics (input t r = t f = 3.0 ns, c l = 50 pf, v cc = 5.0 v, measured in soic package) t a = 25 c symbol characteristic typ max unit v olp quiet output maximum dynamic v ol 0.3 0.8 v v olv quiet output minimum dynamic v ol - 0.3 - 0.8 v v ihd minimum high level dynamic input voltage 3.5 v v ild maximum low level dynamic input voltage 1.5 v
mc74vhc00 http://onsemi.com 4 figure 3. switching waveforms v cc gnd 50% 50% v cc a or b y t phl t plh *includes all probe and jig capacitance figure 4. test circuit c l * test point device under test output figure 5. input equivalent circuit input
mc74vhc00 http://onsemi.com 5 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. -a- -b- g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t -t- f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 soic - 14 d suffix case 751a - 03 issue f
mc74vhc00 http://onsemi.com 6 package dimensions dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l -u- seating plane 0.10 (0.004) -t- ??? ??? ??? section n - n detail e j j1 k k1 detail e f m -w- 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t -v- 14x ref k n n tssop - 14 dt suffix case 948g - 01 issue o
mc74vhc00 http://onsemi.com 7 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 1.42 --- 0.056 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). 0.13 (0.005) m 0.10 (0.004) d z e 1 14 8 7 e a b view p c l detail p m a b c d e e 0.50 m z so - 14 m suffix case 965 - 01 issue o
mc74vhc00 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. typicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 2 - 9 - 1 kamimeguro, meguro - ku, tokyo, japan 153 - 0051 phone : 81 - 3 - 5773- 3850 on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74vhc00/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 - 675- 2175 or 800 - 344- 3860 toll free usa/canada fax : 303 - 675- 2176 or 800 - 344- 3867 toll free usa/canada email : orderlit@onsemi.com n. american technical support : 800 - 282- 9855 toll free usa/canada
|
